The present invention relates to a dynamic memory circuit which requires refresh, and more particularly to a refresh control circuit therein.
Heretofore, dynamic random access memories in which each of the memory cells consists of a MOS FET as a transfer gate and a capacitor have been known as one of a number of popular semiconductor memory devices to be used in an information processing system such as an electronic computer or the like. In this dynamic memory, a stored information "1" or "0" is determined by existence or non-existence of electric charge stored in a capacitor. Such type of memories are fully described, for example, in U.S. Pat. No. 4,045,783. However, in this type of memory, it is necessary to maintain the stored information by recharging the capacitor by rewriting at predetermined time intervals because the charge stored in the capacitor is gradually discharged through a leakage path, e.g., between electrodes thereof. This rewriting is called a "refresh" operation, and the predetermined time interval is called a "refresh period" or "refresh time interval".
In general, the above-mentioned capacitors are formed integrally on a semiconductor substrate constructing a dynamic memory in such a manner that one region in the semiconductor substrate is used as one electrode of the capacitor, an insulator film formed on the substrate is used as a dielectric layer and a conductor layer deposited on the insulator film is used as the other electrode as indicated in U.S. Pat. No. 3,810,125. In this instance, the information stored in each memory cell is maintained in the form of electric charge retained at the boundaries of the dielectric layer and the respective electrodes.
However, this electric charge decreases gradually through a leakage path between the opposite electrodes of the capacitor. The rate of decrease is greatly enhanced as the environmental temperature rises, and accordingly, the refresh time interval must be shortened for compensating the electric charge lost through the leakage path. In prior art memory circuits, however, the refresh time interval has been set at a fixed value. It is to be noted that the shorter the refresh time interval is, the greater is the number of refreshes per unit time. Hence the period of in which the memory is externally accessible decreases, and thus the proportion of availability of the memory is decreased. Therefore the dynamic memory circuits in the prior art had a disadvantage that if the refresh time interval is set so as to meet the worst possible conditions of leakage, then the proportion of availability of the memory circuit is reduced to a minimum.